In the electronics industry, the tendency has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of multiple interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
Typically, the packages on which the integrated semiconductor chips are mounted include a substrate or other chip-mounting device. Substrates are parts that provide a package with mechanical base support and a form of electrical interface that would allow the external world to access the devices housed within the package.
One example of such a substrate is a leadframe. A leadframe typically includes at least an area on which an integrated circuit chip is mounted and multiple power, ground, and/or signal leads to which power, ground, and/or signal sites of the integrated semiconductor die are electronically attached. The area on which the integrated circuit is mounted is typically called a die pad. The multiple leads typically form the outer frame of the leadframe. The die pad is typically connected to the outer frame leads by tiebars so that the whole leadframe is a single integral piece of metal.
In some leadframe configurations, the die pad also serves as the ground plane for the semiconductor package. Recent leadframe development such as Quad Frame No Leads configuration is also proposed to increase density and reduce cost.
In typical leadframe packages, the semiconductor die mounted is smaller than or of the same size of the die pad. In such a configuration, the surrounding leads occupy space where there is no functional semiconductor device. Therefore the density of semiconductor devices on the leadframe is limited. The modern trend of the semiconductor manufacturing and packaging is to increase the device density on the leadframe. Therefore such wasted space in the typical leadframe design presents a problem.
An overhang die approach is proposed to solve this problem. In this approach, the semiconductor die is positioned in such a way that the edge portion of the semiconductor die overhangs the leads of the leadframe. The edge portion of the semiconductor may or may not be in contact with the leads. In so doing, the leadframe could be made smaller and the previously wasted space is utilized because that space is now occupied by the edge portion of the semiconductor die.
However, the overhang approach has various problems. One prominent problem is that in such a configuration it is almost impossible to connect the signal sites on the semiconductor chip to the ground pad on the die pad through wire bonding process because of the overhang configuration. This problem seriously undercuts the advantage that the overhang configuration provides.
Thus, a need still remains for accommodating the modern trend of semiconductor manufacturing and packaging, reducing the package footprint, maximizing the die size, increasing the packaging density, and facilitating interconnections within semiconductor packages. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.